Scopus İndeksli Yayınlar Koleksiyonu / Scopus Indexed Publications Collection

Permanent URI for this collectionhttps://hdl.handle.net/11147/7148

Browse

Filters

20252

Settings

Publisher: search.filters.publisher.IEEE Computer Soc

Search Results

Now showing 1 - 2 of 2
  • Conference Object
    Avoidance of Feature Configuration Faults in Software Product Lines
    (IEEE Computer Soc, 2025) Ergun, Burcu; Tuglular, Tugkan; Belli, Fevzi
    This paper presents a validation approach to feature selection in software product lines (SPL). SPLs consist of similar products tailored to different needs, while SPLs sharing a common platform where feature configurations define product families. Validating feature configurations is critical to avoid defective shipments, recalls, and disposal. Exhaustive, pairwise, and combinatorial testing, among others, aim at ensuring configuration correctness. This paper introduces a novel method for improving feature selection and validation in SPLs by minimizing redundancy while ensuring configurations align with customer needs. The method emphasizes uncovering the differences in feature structures through "complex" and "simple" models, which helps identify and helps identify and tolerate potential errors arising from incorrect feature configurations. This ensures broader coverage while effectively managing dependencies. A case study using the Access Point (AP) SPL model, which is a networking device designed to enhance the strength of an existing wireless signal and expand its coverage area. The AP can enable or disable specific features on AP SPL depending on the characteristics of the third-party gateway with which it is integrated. AP SPL model with 66 features lead to 266 configurations, generated by Exhaustive Testing. Pairwise testing achieves 87% coverage with 132 test cases, while combinatorial testing reaches 94% with 45,760 cases. Our method ensures 100% feature coverage with just 3 test configurations. Thus, the approach introduced in this paper enhances product quality while reducing costs by avoiding redundant tests, making the approaches valuable for large-scale SPLs.
  • Conference Object
    Teaching Accelerated Computing with Hands-On Experience
    (IEEE Computer Soc, 2025) Oz, Isil; Iheme, Leonardo O.
    Heterogeneous computing systems maintain high-performance executions with parallel hardware resources. Graphics Processing Units (GPUs) with many parallel efficient cores and high-bandwidth memory structures enable accelerated computing for high-performance, deep learning, and embedded programs from diverse domains. The expertise in GPU programming requires a significant effort to utilize parallel computational units efficiently. Teaching programming for heterogeneous systems also becomes difficult due to dedicated hardware requirements and up-to-date course materials. In this paper, we present our teaching experience in an undergraduate parallel programming course, where we adopt NVIDIA Deep Learning Institute workshop and teaching kit contents and GPU devices at different scales to expose students to a set of hardware platforms with hands-on coding experience.