Computer Engineering / Bilgisayar Mühendisliği
Permanent URI for this collectionhttps://hdl.handle.net/11147/10
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Conference Object Citation - Scopus: 3Towards Uniform Modeling and Holistic Testing of Hardware and Software(Institute of Electrical and Electronics Engineers Inc., 2019) Kılınççeker, Onur; Belli, FevziThis paper introduces an approach to uniform modeling and testing of hardware and software systems and their faults. As an example, for hardware under consideration, designs at a behavioral level will be used, implemented in Hardware Description Language (HDL). For software, an example will be borrowed from a graphical user interface design. Both examples will be modeled by finite state machines. The mutation of these models leads to lucid hardware and software fault models, respectively. Original models and their mutants will then be used to generate test cases for positive testing and negative testing, respectively, forming a holistic test strategy. A positive test is supposed to validate the system under legal (expected, regular) circumstances, whereas a negative test checks the behavior of the system under illegal (unexpected, irregular) situations. Non-trivial examples are used to validate and analyze the approach with respect to uniform modeling and testing capability. © 2019 IEEE.Conference Object Citation - WoS: 10Citation - Scopus: 13Regular Expression Based Test Sequence Generation for Hdl Program Validation(Institute of Electrical and Electronics Engineers Inc., 2018) Kılınççeker, Onur; Türk, Ercüment; Challenger, Moharram; Belli, FevziThis paper proposes a test sequence generation approach for behavioral model validation of sequential circuits implemented in Hardware Description Language (HDL). In the procedure of test sequence generation proposed in this study, Regular Expressions (REs) are utilized to model the behavior of the System Under Test (SUT). First, the HDL program is converted to a Finite State Machine (FSM). Then, the obtained FSM is transformed to RE which is represented by a Syntax Tree (ST). In this way, the test sequence generation problem is simplified to the tree traversal algorithm in which symbol and operator coverage criteria are satisfied. The required tools for test sequence generation are provided to automatize the whole procedure of the proposed approach. Also, a running example, based on a real-life-like Traffic Light Controller (TLC), validates the proposed approach and analyzes its characteristic features.Article Citation - WoS: 7Citation - Scopus: 11Exploiting Model Morphology for Event-Based Testing(Institute of Electrical and Electronics Engineers Inc., 2015) Belli, Fevzi; Beyazıt, MutluModel-based testing employs models for testing. Model-based mutation testing (MBMT) additionally involves fault models, called mutants, by applying mutation operators to the original model. A problem encountered with MBMT is the elimination of equivalent mutants and multiple mutants modeling the same faults. Another problem is the need to compare a mutant to the original model for test generation. This paper proposes an event-based approach to MBMT that is not fixed on single events and a single model but rather operates on sequences of events of length k ≥ 1 and invokes a sequence of models that are derived from the original one by varying its morphology based on k. The approach employs formal grammars, related mutation operators, and algorithms to generate test cases, enabling the following: (1) the exclusion of equivalent mutants and multiple mutants; (2) the generation of a test case in linear time to kill a selected mutant without comparing it to the original model; (3) the analysis of morphologically different models enabling the systematic generation of mutants, thereby extending the set of fault models studied in related literature. Three case studies validate the approach and analyze its characteristics in comparison to random testing and another MBMT approach.Conference Object Citation - Scopus: 2Towards Test Case Generation for Synthesizable Vhdl Programs Using Model Checker(Institute of Electrical and Electronics Engineers Inc., 2010) Ayav, Tolga; Tuğlular, Tuğkan; Belli, FevziVHDL programs are often tested by means of simulations, relying on test benches written intuitively. In this paper, we propose a formal approach to construct test benches from system specification. To consider the real-time properties of VHDL programs, we first transform them to timed automata and then perform model checking against the properties designated from the specification. Counterexamples returned from the model checker serve as a basis of test cases, i.e. they are used to form a test bench. The approach is demonstrated and complemented by a simple case study.Conference Object Model Based Testing of Vhdl Programs(Institute of Electrical and Electronics Engineers Inc., 2015) Ayav, Tolga; Tuğlular, Tuğkan; Belli, FevziVHDL programs are often validated by means of test benches constructed from formal system specification. To include real-time properties of VHDL programs, the proposed approach first transforms them to concurrently running network of timed automata and then performs model checking on properties taken from the specification. Counterexamples generated by the model checker are used to form a test bench. The approach is validated by a case study composed of a nontrivial application running on a microprocessor. As presented, the approach enables testing both hardware and software at once.Conference Object Citation - WoS: 3Citation - Scopus: 9Boolean Differentiation for Formalizing Myers' Cause-Effect Graph Testing Technique(Institute of Electrical and Electronics Engineers Inc., 2015) Ayav, Tolga; Belli, FevziCause-Effect Graph Testing is a popular technique used for almost four decades. Based on Boolean algebra, this technique assists deriving test cases from a given specification informally written in a natural language. The present paper suggests Boolean differentiation for formalizing this technique. The new approach is applied to an example, borrowed from G. Myers, for demonstrating and analyzing its features. Evaluations show that the new approach outperforms Myers' approach in terms of the detected faults per test cases.Conference Object Citation - Scopus: 5Gui-Based Testing of Boundary Overflow Vulnerability(Institute of Electrical and Electronics Engineers Inc., 2009) Tuğlular, Tuğkan; Müftüoğlu, Can Arda; Kaya, Özgür; Belli, Fevzi; Linschulte, M.Boundary overflows are caused by violation of constraints, mostly limiting the range of internal values of a program, and can be provoked by an intruder to gain control of or access to stored data. In order to countermeasure this well-known vulnerability issue, this paper focuses on input validation of graphical user interfaces (GUI). The approach proposed generates test cases for numerical inputs based on GUI specification through decision tables. If boundary overflow error(s) are detected, the source code will be analyzed to localize and correct the encountered error(s) automatically.Conference Object Citation - WoS: 5Citation - Scopus: 6The 1st Workshop on Model-Based Verification & Validation: Directed Acyclic Graph Modeling of Security Policies for Firewall Testing(Institute of Electrical and Electronics Engineers Inc., 2009) Tuğlular, Tuğkan; Kaya, Özgür; Müftüoğlu, Can Arda; Belli, FevziCurrently network security of institutions highly depend on firewalls, which are used to separate untrusted network from trusted one by enforcing security policies. Security policies used in firewalls are ordered set of rules where each rule is represented as a predicate and an action. This paper proposes modeling of firewall rules via directed acyclic graphs (DAG), from which test cases can be automatically generated for firewall testing. The approach proposed follows test case generation algorithm developed for event sequence graphs. Under a local area network setup with the aid of a specifically developed software for this purpose, generated test cases are converted to network test packets, test packets are sent to the firewall under test (FUT), and sent packets are compared with passed packets to determine test result.Conference Object Citation - Scopus: 3Protocol-Based Testing of Firewalls(Institute of Electrical and Electronics Engineers Inc., 2009) Tuğlular, Tuğkan; Belli, FevziA firewall is the most important tool of network security defense. Its proper functioning is critical to the network it protects. Therefore a firewall should be tested rigorously with respect to its implemented network protocols and security policy specification. We propose a combined approach for test case generation to uncover errors both in firewall software and in its configuration. In the proposed approach, abstract test cases are generated by mutating event sequence graph model of chosen network protocol and filled with values from policy specification by using equivalence partitioning and boundary value analysis. A case study is presented to validate the presented approach.Conference Object Citation - Scopus: 9Event-Based Input Validation Using Design-By Patterns(Institute of Electrical and Electronics Engineers Inc., 2009) Tuğlular, Tuğkan; Müftüoğlu, Can Arda; Belli, Fevzi; Linschulte, M.This paper proposes an approach for validation of numerical inputs based on graphical user interfaces (GUI) that are modeled and specified by event sequence graphs (ESG). For considering complex structures of input data, ESGs are augmented by decision tables and patterns of design by contract (DbC). The approach is evaluated by experiments on boundary overflows, which occur when input values violate the range of specified values. Furthermore, a tool is presented that implements our approach enabling a semiautomatically detection of boundary overflow errors and suggesting correction steps based on DbC.