Computer Engineering / Bilgisayar Mühendisliği

Permanent URI for this collectionhttps://hdl.handle.net/11147/10

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Now showing 1 - 10 of 11
  • Conference Object
    Citation - WoS: 3
    Citation - Scopus: 2
    Heterogeneous Modeling and Testing of Software Product Lines
    (IEEE, 2021) Belli, Fevzi; Tuğlular, Tuğkan; Ufuktepe, Ekincan
    Software product line (SPL) engineering is a widely accepted approach to systematically realizing software reuse in an industrial environment. Feature models, a centerpiece of most SPL engineering techniques, are appropriate to model the variability and the structure of SPLs, but not their behavior. This paper uses the idea to link feature modeling to model-based behavior modeling and to determine the test direction (top-down or bottom-up) based on the variability binding. This heterogeneous modeling enables a holistic system testing for validating both desirable (positive) and undesirable (negative) properties of the SPL and variants. The proposed approach is validated by a non-trivial example and evaluated by comparison.
  • Conference Object
    Citation - WoS: 10
    Citation - Scopus: 12
    Random Test Generation From Regular Expressions for Graphical User Interface (gui) Testing
    (Institute of Electrical and Electronics Engineers, 2019) Kılınççeker, Onur; Silistre, Alper; Challenger, Moharram; Belli, Fevzi
    Generation of test sequences, that is, (user) inputs - expected (system) outputs, is an important task of testing of graphical user interfaces (GUI). This work proposes an approach to randomly generate test sequences that might he used for comparison with existing GUI testing techniques to evaluate their efficiency. The proposed approach first models CUI under test by a finite state machine (FSM) and then converts it to a regular expression (RE). A tool based on a special technique we developed analyzes the RE to fulfill missing context information such as the position of a symbol in the RE. The result is a context table representing the RE. The proposed approach traverses the context table to generate the test sequences. To do this, the approach repeatedly selects a symbol in the table, starting from the initial symbol, in a random manner until reaching a special, finalizing symbol for constructing a test sequence. Thus, the approach uses a symbol coverage criterion to assess the adequacy of the test generation. To evaluate the approach, mutation testing is used. The proposed technique is to a great extent implemented and is available as a tool called PQ-Ran Test (PQ-analysis based Random Test Generation). A case study demonstrates the proposed approach and analyzes its effectiveness by mutation testing.
  • Conference Object
    Citation - WoS: 7
    Citation - Scopus: 8
    Models in Graphical User Interface Testing: Study Design
    (Institute of Electrical and Electronics Engineers, 2020) Silistre, Alper; Kılınççeker, Onur; Belli, Fevzi; Challenger, Moharram; Kardaş, Geylani
    Model-based GUI testing is an important concept in Software GUI testing. Manual testing is a time-consuming labor and heavily error-prone. It has several well-accepted models that Software Testing community has been working and contributing to them for many years. This paper reviews different models used in model-based GUI testing and presents a case study with a proposed approach for how to convert several well-accepted models to ESG (Event Sequence Graphs) to generate test cases and execute them with an aim to consolidate past and future works in a single model. © 2020 IEEE.
  • Conference Object
    Citation - WoS: 1
    Citation - Scopus: 1
    Mutation Operators for Decision Table-Based Contracts Used in Software Testing
    (Institute of Electrical and Electronics Engineers, 2020) Khalilov, Abbas; Tuğlular, Tuğkan; Belli, Fevzi
    The Design by Contract technique allows developers to improve source code with contracts, and testing using contracts helps to identify faults. However, the source code of the program under test is not always available. With black-box testing, it is possible to generate contracts from specifications of the software. In this paper, we apply mutation analysis on a model of a given specifications, where mutants are initially gained by applying proposed in this paper certain mutation operators on corresponding model, and then mutated specifications are examined. © 2020 IEEE.
  • Conference Object
    Citation - Scopus: 3
    Towards Uniform Modeling and Holistic Testing of Hardware and Software
    (Institute of Electrical and Electronics Engineers Inc., 2019) Kılınççeker, Onur; Belli, Fevzi
    This paper introduces an approach to uniform modeling and testing of hardware and software systems and their faults. As an example, for hardware under consideration, designs at a behavioral level will be used, implemented in Hardware Description Language (HDL). For software, an example will be borrowed from a graphical user interface design. Both examples will be modeled by finite state machines. The mutation of these models leads to lucid hardware and software fault models, respectively. Original models and their mutants will then be used to generate test cases for positive testing and negative testing, respectively, forming a holistic test strategy. A positive test is supposed to validate the system under legal (expected, regular) circumstances, whereas a negative test checks the behavior of the system under illegal (unexpected, irregular) situations. Non-trivial examples are used to validate and analyze the approach with respect to uniform modeling and testing capability. © 2019 IEEE.
  • Conference Object
    Citation - WoS: 10
    Citation - Scopus: 13
    Regular Expression Based Test Sequence Generation for Hdl Program Validation
    (Institute of Electrical and Electronics Engineers Inc., 2018) Kılınççeker, Onur; Türk, Ercüment; Challenger, Moharram; Belli, Fevzi
    This paper proposes a test sequence generation approach for behavioral model validation of sequential circuits implemented in Hardware Description Language (HDL). In the procedure of test sequence generation proposed in this study, Regular Expressions (REs) are utilized to model the behavior of the System Under Test (SUT). First, the HDL program is converted to a Finite State Machine (FSM). Then, the obtained FSM is transformed to RE which is represented by a Syntax Tree (ST). In this way, the test sequence generation problem is simplified to the tree traversal algorithm in which symbol and operator coverage criteria are satisfied. The required tools for test sequence generation are provided to automatize the whole procedure of the proposed approach. Also, a running example, based on a real-life-like Traffic Light Controller (TLC), validates the proposed approach and analyzes its characteristic features.
  • Report
    Transforming Vhdl To Timed Automata
    (Izmir Institute of Technology, 2016) Ayav, Tolga; Tuğlular, Tuğkan; Belli, Fevzi
    This report presents the transformation of behavioral VHDL programs to Timed Automata.
  • Conference Object
    Citation - Scopus: 2
    Towards Test Case Generation for Synthesizable Vhdl Programs Using Model Checker
    (Institute of Electrical and Electronics Engineers Inc., 2010) Ayav, Tolga; Tuğlular, Tuğkan; Belli, Fevzi
    VHDL programs are often tested by means of simulations, relying on test benches written intuitively. In this paper, we propose a formal approach to construct test benches from system specification. To consider the real-time properties of VHDL programs, we first transform them to timed automata and then perform model checking against the properties designated from the specification. Counterexamples returned from the model checker serve as a basis of test cases, i.e. they are used to form a test bench. The approach is demonstrated and complemented by a simple case study.
  • Conference Object
    Citation - WoS: 3
    Citation - Scopus: 9
    Boolean Differentiation for Formalizing Myers' Cause-Effect Graph Testing Technique
    (Institute of Electrical and Electronics Engineers Inc., 2015) Ayav, Tolga; Belli, Fevzi
    Cause-Effect Graph Testing is a popular technique used for almost four decades. Based on Boolean algebra, this technique assists deriving test cases from a given specification informally written in a natural language. The present paper suggests Boolean differentiation for formalizing this technique. The new approach is applied to an example, borrowed from G. Myers, for demonstrating and analyzing its features. Evaluations show that the new approach outperforms Myers' approach in terms of the detected faults per test cases.
  • Conference Object
    Citation - WoS: 5
    Citation - Scopus: 6
    The 1st Workshop on Model-Based Verification & Validation: Directed Acyclic Graph Modeling of Security Policies for Firewall Testing
    (Institute of Electrical and Electronics Engineers Inc., 2009) Tuğlular, Tuğkan; Kaya, Özgür; Müftüoğlu, Can Arda; Belli, Fevzi
    Currently network security of institutions highly depend on firewalls, which are used to separate untrusted network from trusted one by enforcing security policies. Security policies used in firewalls are ordered set of rules where each rule is represented as a predicate and an action. This paper proposes modeling of firewall rules via directed acyclic graphs (DAG), from which test cases can be automatically generated for firewall testing. The approach proposed follows test case generation algorithm developed for event sequence graphs. Under a local area network setup with the aid of a specifically developed software for this purpose, generated test cases are converted to network test packets, test packets are sent to the firewall under test (FUT), and sent packets are compared with passed packets to determine test result.