Computer Engineering / Bilgisayar Mühendisliği
Permanent URI for this collectionhttps://hdl.handle.net/11147/10
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Conference Object Citation - Scopus: 3Towards Uniform Modeling and Holistic Testing of Hardware and Software(Institute of Electrical and Electronics Engineers Inc., 2019) Kılınççeker, Onur; Belli, Fevzi; Belli, Fevzi; 03.04. Department of Computer Engineering; 03. Faculty of Engineering; 01. Izmir Institute of TechnologyThis paper introduces an approach to uniform modeling and testing of hardware and software systems and their faults. As an example, for hardware under consideration, designs at a behavioral level will be used, implemented in Hardware Description Language (HDL). For software, an example will be borrowed from a graphical user interface design. Both examples will be modeled by finite state machines. The mutation of these models leads to lucid hardware and software fault models, respectively. Original models and their mutants will then be used to generate test cases for positive testing and negative testing, respectively, forming a holistic test strategy. A positive test is supposed to validate the system under legal (expected, regular) circumstances, whereas a negative test checks the behavior of the system under illegal (unexpected, irregular) situations. Non-trivial examples are used to validate and analyze the approach with respect to uniform modeling and testing capability. © 2019 IEEE.Conference Object Citation - WoS: 10Citation - Scopus: 13Regular Expression Based Test Sequence Generation for Hdl Program Validation(Institute of Electrical and Electronics Engineers Inc., 2018) Kılınççeker, Onur; Belli, Fevzi; Challenger, Moharram; Belli, Fevzi; 03.04. Department of Computer Engineering; 03. Faculty of Engineering; 01. Izmir Institute of TechnologyThis paper proposes a test sequence generation approach for behavioral model validation of sequential circuits implemented in Hardware Description Language (HDL). In the procedure of test sequence generation proposed in this study, Regular Expressions (REs) are utilized to model the behavior of the System Under Test (SUT). First, the HDL program is converted to a Finite State Machine (FSM). Then, the obtained FSM is transformed to RE which is represented by a Syntax Tree (ST). In this way, the test sequence generation problem is simplified to the tree traversal algorithm in which symbol and operator coverage criteria are satisfied. The required tools for test sequence generation are provided to automatize the whole procedure of the proposed approach. Also, a running example, based on a real-life-like Traffic Light Controller (TLC), validates the proposed approach and analyzes its characteristic features.