Computer Engineering / Bilgisayar Mühendisliği
Permanent URI for this collectionhttps://hdl.handle.net/11147/10
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Report Transforming Vhdl To Timed Automata(Izmir Institute of Technology, 2016) Ayav, Tolga; Tuğlular, Tuğkan; Belli, FevziThis report presents the transformation of behavioral VHDL programs to Timed Automata.Conference Object Citation - Scopus: 2Towards Test Case Generation for Synthesizable Vhdl Programs Using Model Checker(Institute of Electrical and Electronics Engineers Inc., 2010) Ayav, Tolga; Tuğlular, Tuğkan; Belli, FevziVHDL programs are often tested by means of simulations, relying on test benches written intuitively. In this paper, we propose a formal approach to construct test benches from system specification. To consider the real-time properties of VHDL programs, we first transform them to timed automata and then perform model checking against the properties designated from the specification. Counterexamples returned from the model checker serve as a basis of test cases, i.e. they are used to form a test bench. The approach is demonstrated and complemented by a simple case study.Conference Object Model Based Testing of Vhdl Programs(Institute of Electrical and Electronics Engineers Inc., 2015) Ayav, Tolga; Tuğlular, Tuğkan; Belli, FevziVHDL programs are often validated by means of test benches constructed from formal system specification. To include real-time properties of VHDL programs, the proposed approach first transforms them to concurrently running network of timed automata and then performs model checking on properties taken from the specification. Counterexamples generated by the model checker are used to form a test bench. The approach is validated by a case study composed of a nontrivial application running on a microprocessor. As presented, the approach enables testing both hardware and software at once.