Öz, Işıl
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Isil, Oz
Oz, I
Oz, I.
Öz, I
Öz, I.
Oz, Isil
Hasırcıoğlu, Işıl
Hasircioglu, Isil
Oz, I
Oz, I.
Öz, I
Öz, I.
Oz, Isil
Hasırcıoğlu, Işıl
Hasircioglu, Isil
Job Title
Email Address
isiloz@iyte.edu.tr
Main Affiliation
03.04. Department of Computer Engineering
Status
Current Staff
ORCID ID
Scopus Author ID
Turkish CoHE Profile ID
Google Scholar ID
WoS Researcher ID
Sustainable Development Goals
1NO POVERTY
0
Research Products
2ZERO HUNGER
0
Research Products
3GOOD HEALTH AND WELL-BEING
0
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4QUALITY EDUCATION
1
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5GENDER EQUALITY
0
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6CLEAN WATER AND SANITATION
0
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7AFFORDABLE AND CLEAN ENERGY
2
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8DECENT WORK AND ECONOMIC GROWTH
0
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9INDUSTRY, INNOVATION AND INFRASTRUCTURE
3
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10REDUCED INEQUALITIES
0
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11SUSTAINABLE CITIES AND COMMUNITIES
0
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12RESPONSIBLE CONSUMPTION AND PRODUCTION
0
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13CLIMATE ACTION
0
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14LIFE BELOW WATER
0
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15LIFE ON LAND
1
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16PEACE, JUSTICE AND STRONG INSTITUTIONS
0
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17PARTNERSHIPS FOR THE GOALS
0
Research Products
Documents
32
Citations
212
h-index
6
This researcher does not have a WoS ID.
Scholarly Output
26
Articles
12
Views / Downloads
12908/4196
Supervised MSc Theses
4
Supervised PhD Theses
0
WoS Citation Count
56
Scopus Citation Count
74
Patents
0
Projects
1
WoS Citations per Publication
2.15
Scopus Citations per Publication
2.85
Open Access Source
12
Supervised Theses
4
| Journal | Count |
|---|---|
| Journal of Supercomputing | 4 |
| 2024 Conference on High Performance Extreme Computing-HPEC-Annual -- SEP 23-27, 2024 -- ELECTR NETWORK | 1 |
| -- 2025 IEEE High Performance Extreme Computing Conference, HPEC 2025 -- Virtual, Online -- 214062 | 1 |
| 2025 International Parallel and Distributed Processing Symposium Workshops-IPDPSW-Annual -- JUN 03-07, 2025 -- Milan, ITALY | 1 |
| ACM Computing Surveys | 1 |
Current Page: 1 / 4
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26 results
Scholarly Output Search Results
Now showing 1 - 10 of 26
Article Citation - WoS: 3Citation - Scopus: 3Regression-Based Prediction for Task-Based Program Performance(World Scientific Publishing, 2019) Öz, Işıl; Bhatti, Muhammad Khurram; Popov, Konstantin; Brorsson, MatsAs multicore systems evolve by increasing the number of parallel execution units, parallel programming models have been released to exploit parallelism in the applications. Task-based programming model uses task abstractions to specify parallel tasks and schedules tasks onto processors at runtime. In order to increase the efficiency and get the highest performance, it is required to identify which runtime configuration is needed and how processor cores must be shared among tasks. Exploring design space for all possible scheduling and runtime options, especially for large input data, becomes infeasible and requires statistical modeling. Regression-based modeling determines the effects of multiple factors on a response variable, and makes predictions based on statistical analysis. In this work, we propose a regression-based modeling approach to predict the task-based program performance for different scheduling parameters with variable data size. We execute a set of task-based programs by varying the runtime parameters, and conduct a systematic measurement for influencing factors on execution time. Our approach uses executions with different configurations for a set of input data, and derives different regression models to predict execution time for larger input data. Our results show that regression models provide accurate predictions for validation inputs with mean error rate as low as 6.3%, and 14% on average among four task-based programs.Master Thesis Compiler-Managed Fault Tolerance Techniques for General Purpose Graphics Processing Units(Izmir Institute of Technology, 2022) Kaya, Ercüment; Öz, Işıl; Öz, IşılAs the use of graphics processing units evolves for general-purpose computations besides inherently-fault tolerant graphics programs, soft error reliability becomes a first-class citizen in program design. In this thesis, we aim to increase the reliability of general-purpose graphics processing units. We propose compiler-based redundancy schemes for graphics processing units. Our framework replicates the annotated kernel function by a programmer at compile time. Our selective redundancy approach enables us to provide full redundancy with no error and partial redundancy with an acceptable error rate with higher performance. We develop different schemes to satisfy the performance and memory requirements of the general-purpose graphics processing unit applications. We build our framework on top of the LLVM compiler framework to increase the reliability of applications that exploit the CUDA programming model and evaluate our schemes for the applications from the PolyBench benchmark suite. We reveal that our partial redundancy approach improves the reliability with a small performance overhead and our full redundancy schemes provide complete fault coverage with varying performance differences based on the application's characteristics.Conference Object Community Detection for Large Graphs on GPUs With Unified Memory(Institute of Electrical and Electronics Engineers Inc., 2024) Dincer, Emre; Öz, Işıl; Oz, IsilWhile GPUs accelerate applications from different domains with different characteristics, processing large datasets gets infeasible on target systems with limited device memory. Unified memory support makes it possible to work with data larger than available GPU memory. However, page migration overhead for executions with irregular memory access patterns, like graph processing workloads, induces severe performance degradation. While memory hints help to deal with page movements by keeping data in suitable memory spaces, coarse-grain configurations can still not avoid migrations for executions having diverse data structures. In this work, we target the state-of-the-art CUDA implementation of the Louvain community detection algorithm and evaluate the impacts of the fine-grained unified memory hints on the performance. Our experimental evaluation shows that memory hints configured for specific data structures reveal significant performance improvements and enable us to work efficiently with large graphs.Article Citation - WoS: 23Citation - Scopus: 31A Survey on Multithreading Alternatives for Soft Error Fault Tolerance(Association for Computing Machinery (ACM), 2019) Öz, Işıl; Arslan, SanemSmaller transistor sizes and reduction in voltage levels in modern microprocessors induce higher soft error rates. This trend makes reliability a primary design constraint for computer systems. Redundant multithreading (RMT) makes use of parallelism in modern systems by employing thread-level time redundancy for fault detection and recovery. RMT can detect faults by running identical copies of the program as separate threads in parallel execution units with identical inputs and comparing their outputs. In this article, we present a survey of RMT implementations at different architectural levels with several design considerations. We explain the implementations in seminal papers and their extensions and discuss the design choices employed by the techniques. We review both hardware and software approaches by presenting the main characteristics and analyze the studies with different design choices regarding their strengths and weaknesses. We also present a classification to help potential users find a suitable method for their requirement and to guide researchers planning to work on this area by providing insights into the future trend.Conference Object Saydam Artıklı Çalıştırma için Vekil Tasarım Örüntüsü Kullanımı(CEUR Workshop Proceedings, 2018) Öz, Dündar; Öz, Sinan; Öz, IşılIn this study, we propose a transparent model for reliable execution of object-oriented software. We design a generic object-oriented programming tool for redundant software execution to provide the desired level of reliability against transient hardware faults. To achieve this, we utilize the Proxy design pattern which is one of the well-known GoF design patterns that are formed to make software systems exible and easy to maintain. Proxy design pattern provides a controlled access and a transparent mechanism for adding new functionalities to an existing object when accessing it. Combining the instruments of dynamic proxy and annotations in Java programming language, we present, Redundant- Caller, a generic, transparent, and con gurable tool for redundant execution and majority voting. Our tool takes any object and creates a dynamic proxy for it which executes the methods of the object multiple times in separate threads, and performs majority voting on the background, requiring minimum amount of change in the original user code. Thanks to annotations, users can con gure the redundant execution scheme methodwise. Our experiments demonstrate that our tool provides a signi cant level of reliability to any object-oriented software with a reasonable amount of performance degradation through multithreaded execution.Publication Quantitative Performance Analysis of Blas Libraries on Gpu Architectures(2024) Öz, IşılBasic Linear Algebra Subprograms (BLAS) are a set of linear algebra routines commonly used by machine learning applications and scientific computing. BLAS libraries with optimized implementations of BLAS routines offer high performance by exploiting parallel execution units in target computing systems. With massively large number of cores, graphics processing units (GPUs) exhibit high performance for computationally-heavy workloads. Recent BLAS libraries utilize parallel cores of GPU architectures efficiently by employing inherent data parallelism. In this study, we analyze GPU-targeted functions from two BLAS libraries, cuBLAS and MAGMA, and evaluate their performance on a single-GPU NVIDIA architecture by considering architectural features and limitations. We collect architectural performance metrics and explore resource utilization characteristics. Our work aims to help researchers and programmers to understand the performance behavior and GPU resource utilization of the BLAS routines implemented by the libraries.Conference Object Citation - WoS: 1Citation - Scopus: 1Gpprmon: Gpu Runtime Memory Performance and Power Monitoring Tool(Springer Science and Business Media Deutschland GmbH, 2024) Topçu,B.; Öz,I.Graphics Processing Units (GPUs) perform highly efficient parallel execution for high-performance computation and embedded system domains. While performance concerns drive the main optimization efforts, power issues become important for energy-efficient GPU executions. While performance profilers and architectural simulators offer statistics about the target execution, they either present only performance metrics in a coarse kernel function level or lack visualization support that enables performance bottleneck analysis or performance-power consumption comparison. Evaluating both performance and power consumption dynamically at runtime and across GPU memory components enables a comprehensive tradeoff analysis for GPU architects and software developers. This paper presents a novel memory performance and power monitoring tool for GPU programs, GPPRMon, which performs a systematic metric collection and offers useful visualization views to track power and performance optimizations. Our simulation-based framework dynamically collects microarchitectural metrics by monitoring individual instructions and reports achieved performance and power consumption information at runtime. Our visualization interface presents spatial and temporal views of the execution. While the first demonstrates the performance and power metrics across GPU memory components, the latter shows the corresponding information at the instruction granularity in a timeline. Our case study reveals the potential usages of our tool in bottleneck identification and power consumption for a memory-intensive graph workload. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2024.Conference Object Teaching Accelerated Computing with Hands-On Experience(IEEE Computer Soc, 2025) Oz, Isil; Iheme, Leonardo O.Heterogeneous computing systems maintain high-performance executions with parallel hardware resources. Graphics Processing Units (GPUs) with many parallel efficient cores and high-bandwidth memory structures enable accelerated computing for high-performance, deep learning, and embedded programs from diverse domains. The expertise in GPU programming requires a significant effort to utilize parallel computational units efficiently. Teaching programming for heterogeneous systems also becomes difficult due to dedicated hardware requirements and up-to-date course materials. In this paper, we present our teaching experience in an undergraduate parallel programming course, where we adopt NVIDIA Deep Learning Institute workshop and teaching kit contents and GPU devices at different scales to expose students to a set of hardware platforms with hands-on coding experience.Conference Object Citation - WoS: 1Citation - Scopus: 2Predicting the Soft Error Vulnerability of Gpgpu Applications(Institute of Electrical and Electronics Engineers Inc., 2022) Topçu, Burak; Öz, IşılAs Graphics Processing Units (GPUs) have evolved to deliver performance increases for general-purpose computations as well as graphics and multimedia applications, soft error reliability becomes an important concern. The soft error vulnerability of the applications is evaluated via fault injection experiments. Since performing fault injection takes impractical times to cover the fault locations in complex GPU hardware structures, prediction-based techniques have been proposed to evaluate the soft error vulnerability of General-Purpose GPU (GPGPU) programs based on the hardware performance characteristics.In this work, we propose ML-based prediction models for the soft error vulnerability evaluation of GPGPU programs. We consider both program characteristics and hardware performance metrics collected from either the simulation or the profiling tools. While we utilize regression models for the prediction of the masked fault rates, we build classification models to specify the vulnerability level of the programs based on their silent data corruption (SDC) and crash rates. Our prediction models achieve maximum prediction accuracy rates of 96.6%, 82.6%, and 87% for masked fault rates, SDCs, and crashes, respectively.Article Citation - WoS: 5Citation - Scopus: 5Regional Soft Error Vulnerability and Error Propagation Analysis for Gpgpu Applications(Springer, 2021) Öz, Işıl; Karadaş, Ömer FarukThe wide use of GPUs for general-purpose computations as well as graphics programs makes soft errors a critical concern. Evaluating the soft error vulnerability of GPGPU programs and employing efficient fault tolerance techniques for more reliable execution become more important. Protecting only the most error-sensitive program regions maintains an acceptable reliability level by eliminating the large performance overheads due to redundant operations. Therefore, fine-grained regional soft error vulnerability analysis is crucial for the systems targeting both performance and reliability. In this work, we present a regional fault injection framework and perform a detailed error propagation analysis to evaluate the soft error vulnerability of GPGPU applications. We evaluate both intra-kernel and inter-kernel vulnerabilities for a set of programs and quantify the severity of the data corruptions by considering metrics other than SDC rates. Our experimental study demonstrates that the code regions inside GPGPU programs exhibit different characteristics in terms of soft error vulnerability and the soft errors corrupting the variables propagate into the program output in several ways. We present the potential impact of our analysis by discussing the usage scenarios after we compile our observations acquired from our empirical work.
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