The Effects of Oxide Thickness on the Interface and Oxide Properties of Metal-Tantalum Pentoxide-Si (mos) Capacitors

Abstract

High dielectric constant tantalum-pentoxide insulating layers were prepared on p-type (100) crystalline silicon wafers using an RF magnetron sputtering technique. Then, metal-oxide-semiconductor (Al-Ta 2O 5-Si) structures were formed with various oxide thickness from 15 to 25 nm. Devices were characterized using the high frequency capacitance-voltage (C-V) spectroscopy method. From the analysis of the high frequency C-V curves, non-ideal effects such as oxide charges and interface trap densities have been evaluated. The results for Ta 2O 5 layers have been compared with those for conventional SiO 2 layers. Interface trap densities were found to be 1.6 ± 0.4×10 12 eV -1 cm -2 for Ta 2O 5 and about 2×10 11 eV -1 cm -2 for SiO 2 insulating layers. There was no clear thickness dependence of the interface trap densities for the Ta 2O 5 insulating layers.