Transforming Vhdl To Timed Automata
| dc.contributor.author | Ayav, Tolga | |
| dc.contributor.author | Tuğlular, Tuğkan | |
| dc.contributor.author | Belli, Fevzi | |
| dc.contributor.author | Ayav, Tolga | |
| dc.contributor.author | Tuğlular, Tuğkan | |
| dc.contributor.other | 03.04. Department of Computer Engineering | |
| dc.contributor.other | 03. Faculty of Engineering | |
| dc.contributor.other | 01. Izmir Institute of Technology | |
| dc.date.accessioned | 2016-12-02T14:18:24Z | |
| dc.date.available | 2016-12-02T14:18:24Z | |
| dc.date.issued | 2016 | |
| dc.description | Technical Report No: IYTE-COMPENG-2015-001 | en_US |
| dc.description.abstract | This report presents the transformation of behavioral VHDL programs to Timed Automata. | en_US |
| dc.identifier.other | IYTE-COMPENG-2015-001 | |
| dc.identifier.uri | https://hdl.handle.net/11147/2571 | |
| dc.language.iso | en | en_US |
| dc.publisher | Izmir Institute of Technology | en_US |
| dc.rights | info:eu-repo/semantics/openAccess | en_US |
| dc.subject | VHDL | en_US |
| dc.subject | Timed automata | en_US |
| dc.title | Transforming Vhdl To Timed Automata | en_US |
| dc.type | Report | en_US |
| dspace.entity.type | Publication | |
| gdc.author.institutional | Ayav, Tolga | |
| gdc.author.institutional | Tuğlular, Tuğkan | |
| gdc.author.institutional | Belli, Fevzi | |
| gdc.author.yokid | 114453 | |
| gdc.author.yokid | 114656 | |
| gdc.coar.access | open access | |
| gdc.coar.type | text::report | |
| gdc.description.department | İzmir Institute of Technology. Computer Engineering | en_US |
| gdc.description.publicationcategory | Diğer | en_US |
| gdc.description.scopusquality | N/A | |
| gdc.description.wosquality | N/A | |
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