Towards Test Case Generation for Synthesizable Vhdl Programs Using Model Checker
| dc.contributor.author | Ayav, Tolga | |
| dc.contributor.author | Tuğlular, Tuğkan | |
| dc.contributor.author | Belli, Fevzi | |
| dc.coverage.doi | 10.1109/SSIRI-C.2010.22 | |
| dc.date.accessioned | 2016-11-30T13:10:53Z | |
| dc.date.available | 2016-11-30T13:10:53Z | |
| dc.date.issued | 2010 | |
| dc.description | 4th IEEE International Conference on Secure Software Integration and Reliability Improvement Companion, SSIRI-C 2010; Singapore; Singapore; 9 June 2010 through 11 June 2010 | en_US |
| dc.description.abstract | VHDL programs are often tested by means of simulations, relying on test benches written intuitively. In this paper, we propose a formal approach to construct test benches from system specification. To consider the real-time properties of VHDL programs, we first transform them to timed automata and then perform model checking against the properties designated from the specification. Counterexamples returned from the model checker serve as a basis of test cases, i.e. they are used to form a test bench. The approach is demonstrated and complemented by a simple case study. | en_US |
| dc.identifier.citation | Ayav, T., Tuğlular, T., and Belli, F. (2010, June 9-11). Towards test case generation for synthesizable VHDL programs using model checker. Paper presneted at the 4th IEEE International Conference on Secure Software Integration and Reliability Improvement Companion. doi:10.1109/SSIRI-C.2010.22 | en_US |
| dc.identifier.doi | 10.1109/SSIRI-C.2010.22 | en_US |
| dc.identifier.doi | 10.1109/SSIRI-C.2010.22 | |
| dc.identifier.isbn | 9780769540870 | |
| dc.identifier.scopus | 2-s2.0-77956097952 | |
| dc.identifier.uri | http://doi.org/10.1109/SSIRI-C.2010.22 | |
| dc.identifier.uri | https://hdl.handle.net/11147/2553 | |
| dc.language.iso | en | en_US |
| dc.publisher | Institute of Electrical and Electronics Engineers Inc. | en_US |
| dc.relation.ispartof | 4th IEEE International Conference on Secure Software Integration and Reliability Improvement Companion, SSIRI-C 2010 | en_US |
| dc.rights | info:eu-repo/semantics/openAccess | en_US |
| dc.subject | Test case generation | en_US |
| dc.subject | Model checking | en_US |
| dc.subject | VHDL | en_US |
| dc.subject | Program transformation | en_US |
| dc.subject | Timed automata | en_US |
| dc.title | Towards Test Case Generation for Synthesizable Vhdl Programs Using Model Checker | en_US |
| dc.type | Conference Object | en_US |
| dspace.entity.type | Publication | |
| gdc.author.institutional | Ayav, Tolga | |
| gdc.author.institutional | Tuğlular, Tuğkan | |
| gdc.author.yokid | 114453 | |
| gdc.author.yokid | 114656 | |
| gdc.bip.impulseclass | C5 | |
| gdc.bip.influenceclass | C5 | |
| gdc.bip.popularityclass | C5 | |
| gdc.coar.access | open access | |
| gdc.coar.type | text::conference output | |
| gdc.collaboration.industrial | false | |
| gdc.description.department | İzmir Institute of Technology. Computer Engineering | en_US |
| gdc.description.endpage | 53 | en_US |
| gdc.description.publicationcategory | Konferans Öğesi - Uluslararası - Kurum Öğretim Elemanı | en_US |
| gdc.description.scopusquality | N/A | |
| gdc.description.startpage | 46 | en_US |
| gdc.description.wosquality | N/A | |
| gdc.identifier.openalex | W2136795009 | |
| gdc.index.type | Scopus | |
| gdc.oaire.diamondjournal | false | |
| gdc.oaire.impulse | 0.0 | |
| gdc.oaire.influence | 3.0438225E-9 | |
| gdc.oaire.isgreen | true | |
| gdc.oaire.keywords | Model checking | |
| gdc.oaire.keywords | Test case generation | |
| gdc.oaire.keywords | Program transformation | |
| gdc.oaire.keywords | VHDL | |
| gdc.oaire.keywords | Timed automata | |
| gdc.oaire.popularity | 5.6573013E-10 | |
| gdc.oaire.publicfunded | false | |
| gdc.oaire.sciencefields | 0202 electrical engineering, electronic engineering, information engineering | |
| gdc.oaire.sciencefields | 02 engineering and technology | |
| gdc.openalex.collaboration | International | |
| gdc.openalex.fwci | 0.0 | |
| gdc.openalex.normalizedpercentile | 0.22 | |
| gdc.opencitations.count | 2 | |
| gdc.plumx.crossrefcites | 2 | |
| gdc.plumx.mendeley | 13 | |
| gdc.plumx.scopuscites | 2 | |
| gdc.scopus.citedcount | 2 | |
| local.message.claim | 2022-06-03T14:19:15.136+0300 | * |
| local.message.claim | |rp00375 | * |
| local.message.claim | |submit_approve | * |
| local.message.claim | |dc_contributor_author | * |
| local.message.claim | |None | * |
| relation.isAuthorOfPublication.latestForDiscovery | 7f52fb71-3121-46a6-a461-2ff1b28d9fa1 | |
| relation.isOrgUnitOfPublication.latestForDiscovery | 9af2b05f-28ac-4014-8abe-a4dfe192da5e |