Model Based Testing of Vhdl Programs
| dc.contributor.author | Ayav, Tolga | |
| dc.contributor.author | Tuğlular, Tuğkan | |
| dc.contributor.author | Belli, Fevzi | |
| dc.coverage.doi | 10.1109/COMPSAC.2015.198 | |
| dc.date.accessioned | 2016-11-29T14:27:35Z | |
| dc.date.available | 2016-11-29T14:27:35Z | |
| dc.date.issued | 2015 | |
| dc.description | 39th IEEE Annual Computer Software and Applications Conference Workshops, COMPSACW 2015; Taichung; Taiwan; 1 July 2015 through 5 July 2015 | en_US |
| dc.description.abstract | VHDL programs are often validated by means of test benches constructed from formal system specification. To include real-time properties of VHDL programs, the proposed approach first transforms them to concurrently running network of timed automata and then performs model checking on properties taken from the specification. Counterexamples generated by the model checker are used to form a test bench. The approach is validated by a case study composed of a nontrivial application running on a microprocessor. As presented, the approach enables testing both hardware and software at once. | en_US |
| dc.identifier.citation | Ayav, T., Tuğlular, T., and Belli, F.(2015, July 1-5). Model based testing of VHDL programs. Paper presented at the 39th IEEE Annual Computer Software and Applications Conference Workshops, COMPSACW 2015. doi:10.1109/COMPSAC.2015.198 | en_US |
| dc.identifier.doi | 10.1109/COMPSAC.2015.198 | en_US |
| dc.identifier.doi | 10.1109/COMPSAC.2015.198 | |
| dc.identifier.isbn | 9781467365635 | |
| dc.identifier.issn | 0730-3157 | |
| dc.identifier.scopus | 2-s2.0-84962128875 | |
| dc.identifier.uri | http://doi.org/10.1109/COMPSAC.2015.198 | |
| dc.identifier.uri | https://hdl.handle.net/11147/2548 | |
| dc.language.iso | en | en_US |
| dc.publisher | Institute of Electrical and Electronics Engineers Inc. | en_US |
| dc.relation.ispartof | 39th Annual Computer Software and Applications Conference Workshops, COMPSACW 2015 | en_US |
| dc.rights | info:eu-repo/semantics/openAccess | en_US |
| dc.subject | Model based testing | en_US |
| dc.subject | VHDL | en_US |
| dc.subject | Timed automata | en_US |
| dc.subject | Model checking | en_US |
| dc.subject | Engineering controlled terms | en_US |
| dc.title | Model Based Testing of Vhdl Programs | en_US |
| dc.type | Conference Object | en_US |
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| gdc.author.institutional | Ayav, Tolga | |
| gdc.author.institutional | Tuğlular, Tuğkan | |
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| gdc.description.department | İzmir Institute of Technology. Computer Engineering | en_US |
| gdc.description.endpage | 432 | en_US |
| gdc.description.publicationcategory | Konferans Öğesi - Uluslararası - Kurum Öğretim Elemanı | en_US |
| gdc.description.scopusquality | Q4 | |
| gdc.description.startpage | 427 | en_US |
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| gdc.oaire.keywords | Model checking | |
| gdc.oaire.keywords | Model based testing | |
| gdc.oaire.keywords | VHDL | |
| gdc.oaire.keywords | Timed automata | |
| gdc.oaire.keywords | Engineering controlled terms | |
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