Osek/vdx Uyumlu Katı Gerçek-zamanlı İşletim Sistemleri için Zamanlama Mimarilerinin Değerlendirilmesi
| dc.contributor.author | Saydam, Berkay | |
| dc.contributor.author | Ayav, Tolga | |
| dc.coverage.doi | 10.1109/UYMS50627.2020.9247064 | |
| dc.date.accessioned | 2021-01-24T18:28:59Z | |
| dc.date.available | 2021-01-24T18:28:59Z | |
| dc.date.issued | 2020 | |
| dc.description.abstract | Developing technology is reflected to the vehicles as well. But it brings the challenge of adding new functionalities to vehicles without compromising safety. The chips, which are used to provide the functionalities, are determined in the first step of ECU design. This decision will effect the remaining part of the development. Designing hardware and software together with testing phase is a long process in automotive industry. Changing the design of the hardware is quite costly after an ECU begins to be used in field. For these reasons, the selection of chips is directly related to cost and the functionality which should be provided to customer. Tasks, which fulfill desired functionality, provide a balance between performance and safety. These were evaluated for an OSEK/VDX certified OS and results are presented from the scheduling algorithms point of view. © 2020 IEEE. | en_US |
| dc.identifier.doi | 10.1109/UYMS50627.2020.9247064 | en_US |
| dc.identifier.isbn | 978-172818541-5 | |
| dc.identifier.scopus | 2-s2.0-85097533585 | |
| dc.identifier.uri | https://doi.org/10.1109/UYMS50627.2020.9247064 | |
| dc.identifier.uri | https://hdl.handle.net/11147/9892 | |
| dc.language.iso | tr | en_US |
| dc.publisher | IEEE | en_US |
| dc.relation.ispartof | 2020 Turkish National Software Engineering Symposium (UYMS) | en_US |
| dc.rights | info:eu-repo/semantics/openAccess | en_US |
| dc.subject | Operating systems (Computers) | en_US |
| dc.subject | Real-time data processing | en_US |
| dc.subject | Automotive industry | en_US |
| dc.subject | Scheduling algorithms | en_US |
| dc.subject | Automotive Safety Integrity Levels | en_US |
| dc.title | Osek/vdx Uyumlu Katı Gerçek-zamanlı İşletim Sistemleri için Zamanlama Mimarilerinin Değerlendirilmesi | en_US |
| dc.title.alternative | Evaluation of Scheduling Architectures for Osek/Vdx Compliant Hard Real-Time Operating Systems | en_US |
| dc.type | Conference Object | en_US |
| dspace.entity.type | Publication | |
| gdc.author.institutional | Ayav, Tolga | |
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| gdc.description.department | İzmir Institute of Technology. Computer Engineering | en_US |
| gdc.description.endpage | 6 | |
| gdc.description.publicationcategory | Konferans Öğesi - Ulusal - Kurum Öğretim Elemanı | en_US |
| gdc.description.scopusquality | N/A | |
| gdc.description.startpage | 1 | |
| gdc.description.wosquality | N/A | |
| gdc.identifier.openalex | W3106379851 | |
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